D&T May-June 2006 - Call for Papers

CALL FOR PAPERS FOR MAY-JUNE 2006

Overview

IEEE Design & Test seeks original manuscripts for a special issue on System-in-Package Design and Test, scheduled for May-June 2006.

Electronic packages provide a means of interconnecting, powering, cooling, and protecting IC chips. This is done through interconnections between active devices, such as IC die or other discrete components, on the package. Integrating digital logic, flash memory, DRAM, analog, and RF blocks on a single SoC to meet the high demands of today’s small and low-cost consumer products has become increasingly difficult. System-in-package (SiP) design and test is a viable, rapid, and cost-effective solution to high-density system integration in a single package. Today’s SiP technology involves the system integration of multiple die from various technologies into a common package. This system integration can reduce form factor, improve performance, accelerate time to market, and reduce power consumption. The most critical challenges for creating SiPs today are the methods and solutions for design and test. Design automation methodologies for rapid deployment in SiPs and test technologies for SiPs are required to produce SiP products.

Because of the increasing importance of SiPs in the accelerated time-to-market business world, IEEE D&T will publish a special issue in this area. Suggested topics for this special issue include

Development and application of EDA tools, including integration of mixed-signal and RF chips;
Integration of known good die, especially in consideration of signal integrity;
Electrical and thermal modeling of SiPs, including interconnect modeling and simultaneous switching noise (SSN) and clock distribution networks;
SiP system integration methodologies, measurements, and characterizations;
RF SiP developments, including integration of embedded passives at the SiP substrate level;
SiP applications, especially in the computer and telecommunication areas;
SiP test methodologies, including SiP substrate testing for defects, and at-speed and functional testing at all levels of integration; and
SiP package characterizations, such as de-embedding techniques and parasitic effects.

Author Information

top

To submit a manuscript, please access Manuscript Central, http://cs-ieee.manuscriptcentral.com, and select “System-in-Package Design and Test.” If you wish to be a reviewer, please contact
dt-ma@computer.org.

The submissions schedule is as follows:

15 December 2005: Deadline for manuscript submissions.
20 January 2006: Authors notified of acceptance with requested revisions.
17 February 2006: Final copy due to dt-ma@computer.org.

Acceptable file formats include MS Word, ASCII or plain text, PDF, and PostScript. Manuscripts should not exceed 5,000 words (with each average-size figure counting as 150 words toward this limit), including references and biographies; this amounts to about 4,200 words of text and five figures. Manuscripts must be doubled-spaced, on A4 or 8.5-by-11 inch pages, and type size must be at least 11 points. Please include all figures and tables, as well as a cover page with author contact information (name, postal address, phone, fax, and e-mail address) and a 150-word abstract. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere, and all manuscripts must be cleared for publication. Accepted articles will be edited for structure, style, clarity, and readability. Please read IEEE Design & Test author guidelines at http://www.computer.org/dt/author.htm.

For more information, visit us on the web at: http://www.computer.org/dt/

TTTC's Electronic Broadcasting Service
	Design & Test of Computers Call for Papers for May-June 2006 Special Issue on System-in-Package Design and Test Guest Editors: Yervant Zorian (Virage Logic) and Bruce C. Kim (University of Alabama) http://www.computer.org/dt/

CALL FOR PAPERS FOR MAY-JUNE 2006
Overview -- Author Information
Overview	top
IEEE Design & Test seeks original manuscripts for a special issue on System-in-Package Design and Test, scheduled for May-June 2006. Electronic packages provide a means of interconnecting, powering, cooling, and protecting IC chips. This is done through interconnections between active devices, such as IC die or other discrete components, on the package. Integrating digital logic, flash memory, DRAM, analog, and RF blocks on a single SoC to meet the high demands of today’s small and low-cost consumer products has become increasingly difficult. System-in-package (SiP) design and test is a viable, rapid, and cost-effective solution to high-density system integration in a single package. Today’s SiP technology involves the system integration of multiple die from various technologies into a common package. This system integration can reduce form factor, improve performance, accelerate time to market, and reduce power consumption. The most critical challenges for creating SiPs today are the methods and solutions for design and test. Design automation methodologies for rapid deployment in SiPs and test technologies for SiPs are required to produce SiP products. Because of the increasing importance of SiPs in the accelerated time-to-market business world, IEEE D&T will publish a special issue in this area. Suggested topics for this special issue include Development and application of EDA tools, including integration of mixed-signal and RF chips; Integration of known good die, especially in consideration of signal integrity; Electrical and thermal modeling of SiPs, including interconnect modeling and simultaneous switching noise (SSN) and clock distribution networks; SiP system integration methodologies, measurements, and characterizations; RF SiP developments, including integration of embedded passives at the SiP substrate level; SiP applications, especially in the computer and telecommunication areas; SiP test methodologies, including SiP substrate testing for defects, and at-speed and functional testing at all levels of integration; and SiP package characterizations, such as de-embedding techniques and parasitic effects.
Author Information	top
To submit a manuscript, please access Manuscript Central, http://cs-ieee.manuscriptcentral.com, and select “System-in-Package Design and Test.” If you wish to be a reviewer, please contact dt-ma@computer.org. The submissions schedule is as follows: 15 December 2005: Deadline for manuscript submissions. 20 January 2006: Authors notified of acceptance with requested revisions. 17 February 2006: Final copy due to dt-ma@computer.org. Acceptable file formats include MS Word, ASCII or plain text, PDF, and PostScript. Manuscripts should not exceed 5,000 words (with each average-size figure counting as 150 words toward this limit), including references and biographies; this amounts to about 4,200 words of text and five figures. Manuscripts must be doubled-spaced, on A4 or 8.5-by-11 inch pages, and type size must be at least 11 points. Please include all figures and tables, as well as a cover page with author contact information (name, postal address, phone, fax, and e-mail address) and a 150-word abstract. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere, and all manuscripts must be cleared for publication. Accepted articles will be edited for structure, style, clarity, and readability. Please read IEEE Design & Test author guidelines at http://www.computer.org/dt/author.htm.
For more information, visit us on the web at: http://www.computer.org/dt/